# About the clock signal

**URL:** <https://forums.digi.com/t/about-the-clock-signal/6105>\
**Category:** NET+OS\
**Created:** [May 23, 2003, 2:55am UTC](https://forums.digi.com/t/about-the-clock-signal/6105 "2003-05-23T02:55:58Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Harold](https://avatars.discourse-cdn.com/v4/letter/h/8491ac/32.png) [@Harold](https://forums.digi.com/u/Harold)\
**Post date:** [May 23, 2003, 2:55am UTC](https://forums.digi.com/t/about-the-clock-signal/6105/1 "2003-05-23T02:55:58Z")

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I am designing my own board based on ns7520. I have removed the CY2309,and direct connect the CLK of the CPU to the SDRAM’s CLK. Can my board work? Because I think the CY2309 only provide multi clk singals. But I only use one clk signals.

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**Author:** ![system](https://us1.discourse-cdn.com/flex016/uploads/digi/original/1X/11da31a6a1fbcd03ef21d3f785c317c824009ae2.png) [@system](https://forums.digi.com/u/system)\
**Post date:** [October 20, 2004, 6:06pm UTC](https://forums.digi.com/t/about-the-clock-signal/6105/2 "2004-10-20T18:06:36Z")

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There are two clocks - the XTAL source and BCLK BCLK connects directly to the SDRAM and is different from the clk/pll source for the NS7520