# Net+50 manual SRAM timings?

**URL:** <https://forums.digi.com/t/net-50-manual-sram-timings/6116>\
**Category:** NET+OS\
**Created:** [February 4, 2004, 10:30pm UTC](https://forums.digi.com/t/net-50-manual-sram-timings/6116 "2004-02-04T22:30:16Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![waster](https://avatars.discourse-cdn.com/v4/letter/w/90db22/32.png) [@waster](https://forums.digi.com/u/waster)\
**Post date:** [February 4, 2004, 10:30pm UTC](https://forums.digi.com/t/net-50-manual-sram-timings/6116/1 "2004-02-04T22:30:16Z")

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The 88334850A NET+50 manual describes the chip select option register RSYNC/WSYNC bits as selecting synchronous read/write timings for a chipselect when set… However, the description says OE\*/WE\* active low inside the CSx\* active low period… but the sync SRAM timing diagrams have CSx\* active low inside the OE\*/WE\* active low periods? So what setting for the RSYNC/WSYNC bits do I actually need to have the cycle timing shown in the Sync SRAM timing diagrams of Figures 61/62 (pages 427 - 428)?

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**Author:** ![system](https://us1.discourse-cdn.com/flex016/uploads/digi/original/1X/11da31a6a1fbcd03ef21d3f785c317c824009ae2.png) [@system](https://forums.digi.com/u/system)\
**Post date:** [January 28, 2005, 4:28pm UTC](https://forums.digi.com/t/net-50-manual-sram-timings/6116/2 "2005-01-28T16:28:33Z")

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The Net+50, i believe, is not supported - but the setting would depend upon the requirements of the SRAM - the chip can accommodate either. History has wr/rd inside cs