# Net+50 SRAM timings?

**URL:** <https://forums.digi.com/t/net-50-sram-timings/4521>\
**Category:** NET+OS\
**Created:** [February 4, 2004, 10:32pm UTC](https://forums.digi.com/t/net-50-sram-timings/4521 "2004-02-04T22:32:46Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![waster](https://avatars.discourse-cdn.com/v4/letter/w/90db22/32.png) [@waster](https://forums.digi.com/u/waster)\
**Post date:** [February 4, 2004, 10:32pm UTC](https://forums.digi.com/t/net-50-sram-timings/4521/1 "2004-02-04T22:32:46Z")

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The 88334850A NET+50 manual describes the chip select option register RSYNC/WSYNC bits as selecting synchronous read/write timings for a chipselect when set… However, the description says OE\*/WE\* active low inside the CSx\* active low period… but the sync SRAM timing diagrams have CSx\* active low inside the OE\*/WE\* active low periods? So what setting for the RSYNC/WSYNC bits do I actually need to have the cycle timing shown in the Sync SRAM timing diagrams of Figures 61/62 (pages 427 - 428)?

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**Author:** ![waster](https://avatars.discourse-cdn.com/v4/letter/w/90db22/32.png) [@waster](https://forums.digi.com/u/waster)\
**Post date:** [February 4, 2004, 10:36pm UTC](https://forums.digi.com/t/net-50-sram-timings/4521/2 "2004-02-04T22:36:10Z")

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BTW sorry for posting the same message on both the NET+50 and documentation lists… This is technically a documentation screw up… but thinking about it my answer is more likely to come from the Net+50 list… Regards, Dave

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**Author:** ![waster](https://avatars.discourse-cdn.com/v4/letter/w/90db22/32.png) [@waster](https://forums.digi.com/u/waster)\
**Post date:** [February 10, 2004, 12:59pm UTC](https://forums.digi.com/t/net-50-sram-timings/4521/3 "2004-02-10T12:59:04Z")

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What not replies? I’ll guess I’ll have to suck-it-and-see with a scope monitoring the chip select and control lines ☹