Where is CPU_SUPV Signal?

In the Net+50 Hardware Reference Guide, I read about CPU_SUPV the Signal. This is mentioned only one time and there is no description what it is. I read that it has to do with the operating mode (which is set by the mode bits of the CPSR register), but there is no ‘signal’…

Its probably an internal signal between the ARM core and the NET+ ASIC… indicating when the core is in supervisior mode… either way it probably shouldn’t be in the manual…