I’m trying to determine the behavior of the rabbit 6000 when interrupts of the same level occur simultaneously.
I’ve read through the existing documentation, and I’ve encountered the following language: “There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as “cleared automatically” have their requests cleared when the interrupt is first handled.”
It seems to be implied here that if we have, say, multiple level 2 interrupts, and if their triggers occur simultaneously, that when the current priority level is below 2, their handlers will both be called based on a predefined order.
Thus, an interrupt will not be lost due to coincidences in timing; unless perhaps the ISR is so long running that the associated interrupt is not cleared fast enough.
Is this correct?
I’ve done a bit of research and talked to an experienced embedded programmer, and apparently it can go either way depending on the hardware being used.
Thanks!
Edit:
I figured I should maybe add an example to make things clearer:
Let’s say we have two level two interrupts which are triggered on a rising edge on different pins. A signal is applied to the first pin, and the interrupt priority is raised to level two. We enter the ISR associated with the interrupt, and we start doing something.
While the first ISR is running, and the processor is at priority level 2, the second pin is triggered.
While we know that the first ISR is not stopped because the two interrupts have the same priority, is there a guarantee that the ISR associated with the second interrupt is called when the processor goes back below priority 2?