RCM6700 SPI Port D disfunction

Hello everyone,

     I am trying to get a RCM6700 working with SPI on serial port D. But so far things have not gone well at all!

     I included the code before #use SPI.lib of 

          #define SPI_SER_D
          #define SPI_RXPORT SPI_RX_PC
          #define SPI_CLOCK_DIVISOR 100
          #define CLOCK_PORT D
          #define CLOCK_BIT 0

Now this alone did not make SPI work on port D. I had to use:
BitWrPortI(PDFR,&PDFRShadow,1,0); after I call SPIInit() to set Port D to the alternate function for SPI. That was my first indication that things were not going well.

Now I have discovered that SPI_CLOCK_DIVISOR is definitely not working. I have my oscilloscope hooked up to my board, and I’m seeing that when the clock runs its running at a frequency of 9MHz regardless of what I set the value of Divisor to. I need to slow it down to 5MHz at the most for my application.

Can someone tell me why using Serial Port D (which is supposed to be supported) is so difficult?

The following works on an RCM5700 and should work on the RCM6700.
Attached, please find a dc-119.c example program file. The source code has been updated to include necessary PC4 TXB alternate output set-up as stated in the following paragraph, quoted from SIPinit()'s function help:
The user MUST set up the serial port Tx, Rx and Clk to the desired parallel
I/O bits BEFORE executing any of the functions in the library. Do not forget
to set the Clk pin direction properly: output for master, input for Slave.
Please note that serial port Rx and Clk set up is not demonstrated. Please consult the Rabbit 5000 Microprocessor manual for complete information on setting up parallel port alternate output functions and serial port alternate Rx input selection.

Taken from Samples\SPI\spi_test.c

Modified by M. Turner, Mercury Defense Systems, 12 June 2013

Test program to test SPIWrite function.

            PB7 acts as the CS line
            PB0 is the serial B clock line(SCLK)

            PC4 is the data output(TX or MOSI)
            PC5 is the data input(RX or MISO)

            Writes two bytes with each chip select.

Signals PB7, PB0, PC4, and PC5 are connected to a logic analyzer to verify
signal activity. SCLK (PB0) looks correct, two groups of 8 clock pulses
per chip select.

PROBLEM: No signal activity for TX (PC4) or RX (PC5). Expecting signal on
TX (PC4) which is always logic ‘1’. Signal RX (PC5) is always logic ‘0’ which
seems correct since this program only does a write.

What am I doing wrong?

#class auto

#define SPI_SER_B
#define SPI_CLK_DIVISOR 100

#use “spi.lib”

void main()
char data_out[2];

data_out[0] = 0x25;
data_out[1] = 0xa4;

WrPortI(PCDR, &PCDRShadow, RdPortI(PCDR) | 0x10); // initial Tx idle high
WrPortI(PCDCR, &PCDCRShadow, RdPortI(PCDCR) & 0xEF); // push-pull drive control
WrPortI(PCDDR, &PCDDRShadow, RdPortI(PCDDR) | 0x10); // output direction
WrPortI(PCAHR, &PCAHRShadow, RdPortI(PCAHR) & 0xFC); // select PC4 TXB altenate
WrPortI(PCFR, &PCFRShadow, RdPortI(PCFR) | 0x10); // enable alternate function


BitWrPortI(PBDR, &PBDRShadow, 0, 7); // chip select low
SPIWrite(data_out, 2);
BitWrPortI(PBDR, &PBDRShadow, 1, 7); // chip select high