Hi All I’m trying to get some start up code working on the Net+50 (see the horrid code generated by GCC for a bitfield access below) but all I get is a data abort when the 2nd byte of the system control register is read (i.e. the byte at 0xFFB00001)… mov r2, #-1342177280 ; 0xb0000000 mov r2, r2, asr #8 ldrb r3, [r2, #1] mvn r3, r3, lsl #25 mvn r3, r3, lsr #25 strb r3, [r2, #1] The code which is attempting to turn the SCR USER bit ON is run with the CPU in supervisor mode and so I’m suspecting the Net+50 just doesn’t allow anything but aligned full 32-bit accesses to the SFRs… but I can’t find any info on this in the documentation. I’d be grateful if anyone could point me in the right direction of any info on this subject… or point out any obvious mistakes on my part… Thanks, Dave
I had the same problem accessing other internal registers, I don’t remember which ones now.
… Apparently it turns out that this an un-documented (not in the user manual / data sheet) feature of the SFRs. With the exception (probably) of the UART FIFO registers all the NET+ARM SFRs can only be accessed in full 32-bit aligned chunks. So all the effort a put into generating SFR bit field types and bitfield access macros was a pointless waste of time… I’ve now got to redo them all using just macros to ensure 32bit accesses with the added disadvantage of losing the Lint strong type checking capability the bitfield provided