Hi,
We are using ConnectCore Wi-i.MX51 board (Windows CE 6.0, Digi BSP). We are trying to connect it to our own device as pseudo static RAM.
We are to develop the driver for our device. It is said, we can use up to 6 chip selects for external devices. As some of them can be used somewhere else, we tried all of them (CS0 - CS5) with the same result. MX51 board RESETS when our DRIVER attempts to access the chip select memory space INREG16(addr).
But when we moved our chip select configuring and access to the OAL level (OALLIB modules: startup.s, init.c, etc.) hardware works OK!
Sorry.
The question is just “Where, when and why access via chip select becomes disabled?”
We also tried to include chip select configuring and access into some Digi BSP drivers. In NandFmd driver it works. And in ConfigOS driver it does not.
WinCE uses virtual memory mapping, this means that the memory addresses used inside of applications are all virtual. They do not actually map directly to the hardware.
The easiest way to get access to those registers is to make sure that your driver is running in the kernel. At the kernel level, and is not using virtual memory.
The reason it works in some of our drivers and not others is that some (like the FMD driver) run at the kernel level because they need direct access to hardware pointers. Others (like ConfigOS) don’t rely on that kind of low level access, so they run in virtual memory.
Thanks, but we don’t use SMSC9118 driver in our OSdesign.
The Digi ConnectCore design template has “LAN9221 Ethernet Controller” not selected (BSP_ETHER_LAN9221 not set).
But nevertheless, I’ve found out the problem was in CCGR5 register settings. They were modified somewhere after NandFmd driver initialization, but before the initialization of the next (according to reginit.ini) builtIn driver - ConfigOS.
Hi,
Now when our driver gained access to asynchronous memory, we have some problem in WEIM (chip select configuring).
It looks like the relatively long pauses appear between two (and more) successive read and/or write operations.
We tried a lot of different register settings.
E.g. we used the following settings.
To view access cycle and other signals we used endless loop.
E.g.
while (1)
{
OUTREG16 ( p_AsyncRAM_CSx , data16);
}
We got the periodic CS0 signal of 30ns low and 170ns high (between CS0). I.e. 200ns for each asynchronous memory access. We received the same 170ns interval for various low CS0 durations.
But (as we can see on 63.8.3 Asynchronous Read/Write Memory Accesses Timing Diagram) continuous bus cycles appear almost immediately one after one.