External data bus


I would like to connect this micro to an FPGA using the external data bus.
I’ve been looking through all of the documentation included with the ConnectCore 7U, and I am unable to find any examples of configuration and accessing the external data bus (i.e. Memory Controller Module). Does anyone have any examples? Ideally, I’d like to see an example of configuring the chip select, configuring the SRAM controller (to Asynch R/W), reading a single byte from an address, and writing a byte from an address.

Thanks in advance for any help offered!


I did a project with the 7U back in the days of NetOS 6.0.

This used the data bus in 8 bit mode and had a cople of latches mapped into the address space. I have attached the files that are concerned with the memory interface. There is a lot of extra code in there but I think they contain the basics for setting up the Chip selects and reading memory mapped peripherals.


Hi Rob,

Thanks for your help. With some digging around of some old archives, I think I have figured out the proper way to configure the device - but have still not had any success. When I place a scope on the OE, WE, CS3, ADDR0 signals (X5 connector on eval kit) I see no action! .

I am using netOS 7.3, on digi evalkit.

Below is the code snippets:


// set Size of Memory Map to 0x2000 (8k)
narm_write_reg(NARM_CSOR_REG, NARM_CSOR3_ADDR,mask, customizeCreateMask(0x2000) >> CS_BASE_MASK_SHIFT);
// set wait states
narm_write_reg(NARM_CSOR_REG, NARM_CSOR3_ADDR,wait, 15);
// set 8-bit data
// set base address to be 0x7000000 (dec 117440512)
narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,base, 0x7000000 >> CS_BASE_MASK_SHIFT);
//unset write protect.
narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,wp, FALSE);
// set valid
narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,v, TRUE);

baseAddress = (*NARM_CSAR3_ADDR) & (unsigned long)0xFFFFF800;	
cout << "NARM_CSAR3_ADDR   : " << (*NARM_CSAR3_ADDR) << endl;
cout << "NARM_CSOR3_ADDR   : " << (*NARM_CSOR3_ADDR) << endl;
cout << "NARM_CSORB3_ADDR  : " << (*NARM_CSORB3_ADDR) << endl;
cout << "baseAddress: " << baseAddress << endl;

So I have my 3 registers with the following values (in decimal):
NARM_CSAR3_ADDR : 117440513
NARM_CSOR3_ADDR : 4093636360
baseAddress: 117440512

So I verify that I am setting them correctly.

This is how I am performing my read / write:

unsigned char DataPort::read(int address)
ulong address2 = baseAddress + address;
//next line is debug only
cout << “DataPort::read :” << address2 << " - " << *((unsigned char *) address2) << endl;
return *((unsigned char *)address2);

so if I read register addresses 0x00-1FFF (physical address 0x700001 - 0x701FFF), I always read the value 232 (0xE8)

>DataPort::read :117440513 - ë
>ADDRESS 0x1 : 232

So… I see no action on the external bus with my scope, and always read value of 232. So… I must be doing something wrong!

Also, the timing diagrams documented in the NS7520 are not specific to the 7U… The 7U only has a WE and OE signals available, so perhaps there are some more special settings?

Any help appreciated. I’m going to send a copy of this to tech support.

Best Regards,

Hi Me,

FYI, I contacted Digi, and they set me straight:

In reviewing what you sent in I can see a few things wrong. Your port size should be 8 bit (10), instead it’s set to 32 bit (00), you need to set bcyc, the mask you’re using is incorrect, currently it’s set for 0xF3FFE when it should be set for 0x0DFFF (try writing this in the register instead of trying to create the mask). Also, the base address I’ve normally seen used (the one we specify in the programmers guide) is 0x03000000, try using that one instead of 0x07000000 incase the bootstraping is causing a conflict.
One additional piece of information, when you have the debugger attached, it uses the same lines as some of the address lines, so you won’t be able use the debugger and properly read/write (although I would expect to see the WE/OE lines wiggle).

So I have changed my code to:

// set Size of Memory Map to 0x2000 (8k)
narm_write_reg(NARM_CSOR_REG, NARM_CSOR3_ADDR,mask,0x0dfff);
// set 8-bit data

	// set wait states
narm_write_reg(NARM_CSOR_REG, NARM_CSOR3_ADDR,wait, 15);
narm_write_reg(NARM_CSOR_REG, NARM_CSOR3_ADDR, bcyc, 10);
// set base address to be 0x3000000 

narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,base, 0x3000000 &gt;&gt; CS_BASE_MASK_SHIFT);
// unset write protect	
narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,wp, FALSE);
//set valid
narm_write_reg(NARM_CSAR_REG, NARM_CSAR3_ADDR,v, TRUE);

I see some action on the address bus. I’ll need to do some more testing, but I may have this resolved.