Hi All I’m looking into the possibility of producing a bi-directional DMA controlled interface to a serial audio CODEC… A Xilinx CPLD will provide the 8-bit host bus / DMA to bi-directional serial interface logic. The software will need, for 24Khz stereo in and out 16-bit audio, to be able to transfer 1 byte to the interface and 1 byte from the interface every 10.416us… and due to the size of the CPLD it is unlikely there will be much buffering of data so this transfer rate is basically fixed to avoid underrun or overrun errors… My first thought was to use both external memory to memory DMA channels, one for the RAM to CPLD transfer (audio out) and the other for the CPLD to RAM transfer (audio in)… and live with the high context switching overhead of single byte transfers… However, looking at the Net+50 manual it is unclear as to whether both can be enabled at the same time… and also how the control lines work with respect to closing buffers… particularly w.r.t the CPLD -> RAM transfer… Anyone know: 1) If my basic concept is possible? 2) Of any documentation with a better description of the external DMA control lines and the interactions with the DMA channel SFRs and interrupts? Thanks Dave
I’ve been investigating further and I’m still unsure of the following: 1) In ENI mode can both channel 3 (or 5) and channel 4 (or 6) be enabled for external DMA transfers at the same time? The original manual (883324A) sort of indicates yes but the latest manual (8833450A) is more in favor of No… 2) With external peripheral fly by mode, where data is transferred directly between memory and a peripheral, can the memory device be SDRAM?.. or must it be a static device?.. Regards, Dave