generation of /IOWR and /IORD signals

how to generate the /IOWR signal for writting data to I/O peripheral and /IORD signal to reading data from external device.

These signals are generated automatically when you have setup the Aux. I/O bus with an address range, and you execute a RdPortE, WrPortE, or IOE prefixed instruction to one of the addresses within that range. The Aux. I/O bus enable is done through the SPCR register, and the address range or ranges are setup by using one or more I/O Banks through the IBxCR registers. By setting up the bank, you can also get a Strobe or Chip Select signal which is activated by addresses within the range for that bank. If you setup multiple banks, you can address more than one device on the bus without the need for external address logic. Just look for the SPCR and IBxCR registers in the user manual for your processor and the bits you need to control the Aux. I/O bus will be explained.