I have Hardware interrupts on port C that occurs every 100 us (7 us after a Timer2 interrupt). Is it normal that it takes 12 us between the moment that the interrupt occurs and the moment when the first instruction in the ISR is executed ? This works normally for more than 200 timer ticks, and after that, the port C interrupt software is not completely performed and the interrupt isn’t acknowledged so the processor don’t care about all the other interrupts on port c. When I change the timer ticks period to 200 us, the problem appears after more that 400 ticks.
It could be that it is missing at the time when network is highly loaded. Could you repeat it in an isolated network to see if it manifests itself the same way.