I am using Pin Sleep for the XBee and I think a STOP3 mode on the Freescale processer. I am waking the Freescale processor on a digital input change interrupt. I then wakethe XBee if there is enough flip-flopping on the digital input. However, I am not sure this is the lowest power consumption I can get.
Just based on the power supply’s readings, I am still pulling about 10 milliamps.
Is there a way to get it lower?
Is Pin Sleep the lowest power draw for the Digi XBee chip?
Is STOP3 the lowest I can do while still watching the digital input pins to cause an interrupt.
Do I need to turn off the clocks for different components (i.e. IIC) during a STOP3 or are they automatically stopped?
Any helpful hints on pushing the power draw down on the Programmable Variant of the XBee chip is greatly appreciated.
Sorry, can’t answer your question directly. 10mA is pretty bad (battery-wise).
You may need external circuits to wake the freescale on digital change. The freescale is a low-power CPU, but not one designed as explicitly for such battery applications. (My opinion - as a software guy)
I should add, most customer with sleep-draw issues have problems with line pull-up. Remember, hardware pull-up is ‘forever’ unless you disable pull-up during sleep.
Pull-ups enabled within the XBee should correctly be set to float during sleep, but if you have added external pull-up/down, that could be a major source of sleep-current draw.
You should be able to get down in the 2 to 5 uA range.
Make sure you are measuring just the module current, and not all the supporting circuitry if you are using an interface board. The Programmable processor draws about 10mA when not in sleep.
If any line is floating, it may cause up to an extra 500uA of current draw for each line that is floating. Each data line should be driven by the XBEE or external circuitry or have a pull-up enabled to ensure that it is High or Low. Driving a line low that has a pullup enabled will also cause extra current to be drawn.
Xbee pins may need pull-ups during sleep, but I have had several Xbee customers with custom hardware mention that active pull-ups during sleep on external chips which are powered off (aka: vcc/supply is zero) may cause a parasitic load because the I/O pins are now 3vdc higher than Vcc, so pull-ups during sleep may cause the chip OV protection to semi-power up the chip.
True, low-power sleep is a tricky EE design excercise - but bottom line: evaluate the use of pull-ups carefully & do the right thing
