New Register settings?

We are currently in the process of moving to OS5 coming from OS3 and providing for the net50 at the same time. I noticed in NCC_init.c that there is a new setting for the PLL register pllval.bits I cannot find this in any of the manuals or on the website. What is it and are there any other register modifications new or old required? Additionally if the clock is running faster what adjustments do I need to make for the sdram and flash chip select registers as well as the SDram values. I would like to port using the same 33.1776 osc and then cranking it up to the higher speed on an optional populated basis. mike

The SDRAm refresh id adjusted automatically ae the beginning of NCC_INIT. For other chips I think will be necessary to calculate the new number of wait states …