Hi All I notice the old data sheet for the Net+50 has a section for the PLL control register, where as this has been removed in the new manual and replaced by a statement about changing clock speed by using a different crystal… My question is, does this still have to configured? and if so what’s the procedure, considering I’m using a 18.432MHz crystal and I’m hoping to run at full speed bus? Thanks, Dave
PLL Control Register 0xFFB0 0008 The PLL Control Register is changed to reflect 2 things: the different inputs for PLL fine-tuning (now IVCO, ICP -was POLTST, INDIV, ICP, and OUTDIV), and the PLLCNT was hardwired to come up from RESET at 44.2368 MHz internal clock. The PLLCNT value should not be changed from its default (reset) value (‘1001’ binary, or 9), since the PLL’s output frequency should not be allowed to change on the fly. Besides the PLLCNT bits, only the lowest 3 bits are functional in the PLL Control Register for the 50-3. Bit 2 is ICP, with a default setting of 1 (1 seems to specify a 38uA current somewhere and 0 seems to set this current to 9.5uA) Bits 1 and 0 are IVC1 and IVC0, respectively, with a default value of 2 (0b10). This seems to set the frequency range, and we seem to be well inside the stated limits for crystals between 10-18.432 MHz. PLL Control Register Recommended Setting for 50-1 and 50-3 0xFFB00008 = 0x09000E1E
Thanks… I’ve checked and i’m using a rev 1 chip so the register comes up with a default value of 0. Using the value 0x09000E1E appears to work. BTW Is it sufficient to poll the PLL locked bit in the system status register to confirm the PLL is locked when applying the above setting on the rev 1 chip or do I need a hardcoded delay? Thanks Dave