NS7520 clock speed errata

With regard to the “PLL initiailzation” error in the NS7520: The recommended action is for designers to place an invertor (from “reset”) in front of the SCANEN pin. Is there a plan to fix the error in a future mask of the device? Or does the advice apply indefinitely?

The issue will definitely be fixed if there will another respin of the chip yet at the moment there is no such plan.