Hi,We have three STE10/100 PCI Network controllers connected to the PCI-Bus. Whenever the STE10/100 is bus master the master broken bit gets set in the Arbiter Interrupt status register 0xa0300004. The Arbiter does’nt Grant the bus any more until I toggle the master enable bit in a0300000. This causes a very high Interrupt load because this happens 2-10 times per network packet. The documentation says that the master broken bit is set when the master doesn’t respond in 16 Cycles after grant. But the master sets #FRAME to low very soon (about 3-4 cycles after the Request, this should be immediately after GNT) but the master-broken bit is set anyway. I appended three pictures from oscilloscope: 1. The request(ch1)/grant(ch2) picture shows the first and only master Transaction of the STE10/100: After req the bus is granted after 100ns. GNT is released about 700ns after REQ is released. When the STE10/100 requests the bus a second time it will not be granted becaus Master broken bit will be set. 2. The request(ch1)/frame(ch2) picture shows that about 100ns after the request (This should be immediately after GNT) the STE10/100 starts a Frame. (So it does 3. The devsel(ch1)/req(ch2) picture shows that the STE10/100 really addressed the target memory correctly and the NS9750 BAR0 feels selected 200ns after Request, this is 100ns after GNT or 3 PCI-Cycles which is the slow-devsel timing. All requests really work. There are no corrupted network packets. So I don’t understand why the master broken bit gets set. Is there any chance to disable this error detection ? Reeanbling the broken masters on the PCI-Bus eats my CPU time ! Jochen
Hi,I now meassured GNT low to FRAME low of the STE10/100. It is 43ns. This shows that the STE10/100 starts the transaction immediately, but the NS9750 thinks it needed longer than 16 PCI-Cycles. Does anybody know what condition is needed that the NS9750 recognizes the transaction as started ? Jochen
See errata from August 2004: PCI Arbiter senses false request. Jochen