I have a board that (due to power issues) runs at 11Mhz and uses 2MB 16-bit SRAM. The board works fine in general but I can only run the ethernet controller at 10Mb/s. When I try to run at 100Mb/s and tries to ping the board most, but not all, packets are lost. First I thought it was a noise problem so the packet could not be received but if I set a breakpoint at eth_packet_transmit I can see that the packet is not only received but the TCP/IP stack has also called eth_packet_transmit to send a response. The eth_packet_transmit start the DMA and the dma controller starts to copy the data. In the ethernet_tx_isr I can see that the DMA module reports a PCIP interrupt (premature complete interrupt pending) when I don’t get a response and not when a response is sent. The transmit status register in the ethernet module says that the packet was sent ok (TXOK is the only asserted bit) so the ethernet module has not detected any problem. So the questions are simply: What causes the PCIP field in the ethernet tx DMA status register to be asserted and why is not this error handled (no code examines this bit) ? How shall I solve the problem?
the official minimum requirement for 100Mb/s is 40mhz, but even theoreticaly it should be atleast 25mhz (100Mb/s clock)
We have the same issue that is our boards (NetOS 5.0 & GHS 3.5) only works at 10M and not 100M. We running at maximum clock speed. The problem acording to Netsilicon is the RAM size. We also have 2MB. They are now recommending 16MB of RAM for prober operation
The 18mhz clock is internally multiplied to 44Mhz
I know that theoretically the minimum is 25Mhz if there wasn’t any FIFO in the ethernet module, but my packets (it doesn’t even work with ping) are all small enough to fit in the FIFO so shouldn’t the ethernet module be able to handle that? There are bits in the ethernet module that indicates if you get an overrun in the FIFO and that bit does not get asserted as far as I know. The NS7520 development board has a 18Mhz clock, doesn’t that board run at 100Mb/s when you use that clock?
!!! Why does the size of the RAM make any difference? The packets are very small and the RAM does not get full as far as I know. What is the explanation because I don’t want/can’t mount 8 times the RAM just to run the ethernet controller faster ???
I have changed the crystal to 24Mhz. Now it works fine with 100Mb/s full duplex. I only have 2MB of SRAM (16-bit) on my board.
Maybe someone from Netsilicon can explain “clearly” why 16M of RAM is required. I would have expected a “warning” at compile/link time indicating that there was not enough memory.