problems of controlling nand flash

I try to control a 8bits data bus NAND flash (ST NAND128W3A2BN6) by NS7520.
I connect the CLE and the ALE to address bus of NS7520 and IO bus to the data bus of NS7520.

My questions are…

Does any sample codes for controlling NAND flash can be reference?

How to access the value of address and data bus? Would you indicate the section, chapter and document name for me…

thanks a lot. :slight_smile:

I found the yaffscfg2k.c and yaffs_ynand.h.
It seem to support the NAND flash.
I see the supported chip in nandDevice nand_init_tbl[], do you have new code to support STMicro NAND128W3A2BN6?

I try modify the h and c files to match my chip but the commands of chip seem very different each other.

The PAGEPROG command need 2 cycles in W3A2BN6 but the definition of original code is 1 cycle.
I don’t know how to make the PAGEPROG work as 2 cycle.
Should I append a number to the definition to indicate 2nd cycle?
like as
#define PAGEPROG1 0x80
#define PAGEPROG2 0x10

The Read command also different. I have three read function in my chip. The ReadA, ReadB and ReadC to read different area 0~255, 256~211 and 512~527 in page respectively.

I cann’t found the implementation of interface in header file. Should I implement them by my self or check out codes from