Hi,
Is it possible to use SPI with this kind of config ?
#define SPI_MASTER
#define DELAY 2L
#define SPI_MASTER_CS_PORT PEDR //define CS port from master to Slave (PORT E)
#define SPI_MASTER_CS_SHADOW PEDRShadow //define shadow register for CS (Master only)
#define SPI_MASTER_CS_BIT 5 //define CS bit number (PE5)
//#define SPI_SLAVE_RDY_PORT PEDR
//#define SPI_SLAVE_RDY_SHADOW PEDRShadow
#define SPI_SLAVE_RDY_BIT 2
#define SPI_SER_B
#define SPI_CLK_DIVISOR 5
#define SERB_USEPORTD
#define MESSAGE_LENGTH 7
#use “spi.lib”
#define CS_HI BitWrPortI(SPI_MASTER_CS_PORT, &SPI_MASTER_CS_SHADOW, 1,SPI_MASTER_CS_BIT)
#define CS_LO BitWrPortI(SPI_MASTER_CS_PORT, &SPI_MASTER_CS_SHADOW, 0,SPI_MASTER_CS_BIT)