Hi everyone,
I am working on a custom board based on Digi ConnectCore MP157 (STM32MP157). I am facing a persistent issue where the MDIO bus appears completely silent (no clock on MDC and only 3V3 on MDIO) during Linux boot, resulting in PHY detection failures.
Hardware Setup:
-
SoC: STM32MP157
-
Ethernet MAC: internal
stmmac(ETH1), RGMII mode. -
Switch: NXP SJA1105Q connected to the CPU port via RGMII (Fixed Link).
-
MDIO Bus: Managed by the STM32 MAC, shared by 4 PHYs:
-
Addr 0: Analog Devices ADIN1300 (Main LAN)
-
Addr 1: TI DP83TC811 (100BASE-T1)
-
Addr 2: TI DP83TD510E (10BASE-T1L)
-
Addr 3: Microchip LAN8671 (10BASE-T1S)
-
The Problem: In U-Boot, the MDIO bus works correctly. I can use mdio read 0 0 and I see valid traffic on the oscilloscope (MDC clocking, MDIO data moving). However, once Linux boots, the MDC pin remains static (no clock generation), and the kernel fails to detect any PHYs.
Error Logs (dmesg): The SJA1105 driver loads but fails to connect to the PHYs because the MDIO bus read returns nothing (likely reading all zeros).
sja1105 spi0.0: Probed switch chip: SJA1105Q
sja1105 spi0.0: configuring for fixed/rgmii link mode
sja1105 spi0.0 lan0 (uninitialized): failed to connect to PHY: -ENODEV
sja1105 spi0.0 lan0 (uninitialized): error -19 setting up PHY for tree 0, switch 0, port 0
Checking via sysfs shows the devices exist (instantiated by DT), but IDs are invalid:
cat /sys/bus/mdio_bus/devices/stmmac-0:00/phy_id
sja1105 spi0.0: Link is Up - 1Gbps/Full - flow control off
What I have verified/tried:
-
Hardware/Electrical:
-
PHY Reset: All PHY reset pins are confirmed HIGH (3.3V) during Linux boot.
-
PHY Clocks: ADIN1300 has a stable 25MHz clock input.
-
Oscilloscope: In U-Boot, MDC toggles correctly. In Linux, MDC stays low with NO clock activity and no MDIO(only 3V3 pull up) even when forcing a read via userspace.
-
Pinmux: Checked
/sys/kernel/debug/pinctrl/.../pins, PC1 (MDC) and PA2 (MDIO) are correctly set to AF11.
-
-
Device Tree Configuration: I suspect a conflict between the
fixed-link(for the switch) and themdionode, or an issue withsnps,clk-csr.
Current Device Tree Configuration: I suspect there might be a conflict in the stmmac driver when using both a fixed-link (for the data path to the switch) and a standard mdio node (for PHY management).
Current Device Tree Snippet:
&spi6 {
pinctrl-names = “default”, “sleep”;
pinctrl-0 = <&ccmp15_spi6_z_pins>;
pinctrl-1 = <&ccmp15_spi6_z_sleep_pins>;
clocks = <&scmi_clk CK_SCMI_SPI6>;
resets = <&scmi_reset RST_SCMI_SPI6>;
cs-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
status = "okay";
switch@0 {
compatible = "nxp,sja1105q";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpha;
reset-gpios = <&gpiob 10 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&phy0>;
phy-mode = "rgmii";
sja1105,role-mac;
};
port@1 { reg = <1>; label = "lan1"; status = "disabled";};
port@2 { reg = <2>; label = "lan2"; status = "disabled";};
port@3 { reg = <3>; label = "lan3"; status = "disabled";};
port@4 {
reg = <4>;
label = "cpu";
ethernet = <ðernet0>;
phy-mode = "rgmii";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
ðernet0 {
status = “okay”;
pinctrl-names = “default”, “sleep”;
pinctrl-0 = <&ccmp15_ethernet0_pins &mdc_pins &mdio_pins>;
pinctrl-1 = <&ccmp15_ethernet0_sleep_pins>;
phy-mode = "rgmii";
st,ext-phyclk;
snps,clk-csr = <0>;
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&si5351 0>,
<&rcc ETHSTP>;
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "eth-ck", "ethstp";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
/\* === ADIN1300 PHY @ MDIO 0 === \*/
phy0: ethernet-phy@0 {
compatible = "adi,adin1300";
reg = <0>;
/\* RESET pin = PA3 \*/
reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
/\* IRQ pin = PF8 \*/
interrupt-parent = <&gpiof>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
};
};
};
…
…
mdc_pins: mdc-pins {
pins {
pinmux = <STM32_PINMUX(‘C’, 1, AF11)>; /* MDC */
drive-push-pull;
bias-disable;
slew-rate = <2>;
};
};
mdio_pins: mdio-pins {
pins {
pinmux = <STM32_PINMUX(‘A’, 2, AF11)>; /* MDIO */
drive-open-drain;
bias-pull-up;
slew-rate = <0>;
};
};
ccmp15_ethernet0_sleep_pins: ethernet0-rgmii-sleep-0 {
pins1 {
pinmux = …another ethernet pins…
<STM32_PINMUX(‘G’, 4, ANALOG)>, /* GTX_CLK */
<STM32_PINMUX(‘C’, 1, ANALOG)>, /* MDC */
<STM32_PINMUX(‘A’, 2, ANALOG)>, /* MDIO */
<STM32_PINMUX(‘C’, 4, ANALOG)>, /* RXD0 */
…another ethernet pins…
};
};