The CC6UL Hardware Reference Manual describes an “undervoltage detection” without mentioning a specific undervoltage threshold. The PMIC data sheet describes a change from “ON” to “Coin Cell Mode” at an undervoltage threshold UVDET (falling 2.5V) and a LOWVINI interrupt at 2.70V.
As mentioned in question “[CC6UL]: 3.3V input voltage for VSYS and VSYS2”:
“The minimum input voltage documented in the PMIC datasheet is 2.8V, but this input voltage is not enough for powering the whole CC6UL SOM”.
Is there a CC6UL specified VSYS resp. VSYS2 voltage level at which the SoM will go into coincell mode? (front LDO used)
Have you seen this page of module’s HRM?
There are two tables there that should answer your questions. If not let me know and I will look deeper.
Thank you for the quick answer.
From your link the table “With front-end LDO” I can see that the minimum voltage of VPWR > 3.7V is sufficient to keep the CC6UL alive. (For this reason I am surprised that in the line below the minimum VSYS voltage is 4.3V instead of 3.7V, because VSYS and VSYS2 are downstream of the MOSFET and VPWR).
Regardless of this my main concern is that I don’t know what should happen if my main power supply slowly drops and the critical voltage level VPWR = 3.7V is reached. My own measurements have shown that the CC6UL will detect a power supply shortage at a threshold in the 3.7V range and PWR_ON is driven low (presumably by the MCA).I haven’t found this behavior in the documentation yet (e.g. interrupts in the PMIC datasheet) and wonder if it is a specified procedure and if there is any info about it?