I am using BL2600’s Analog Outputs and find that the outputs are enabled for about two seconds before settling down.
What is the best initialization practice to minimize Analog Outputs from spiking during power up.
As Tested ***********************************************************
brdInit(); // init controller
_sysIsSoftReset(); // restore any protected variables
anaOutConfig(DAC_UNIPOLAR, DAC_ASYNC); // config DAC for unipolor 0 to +10V output
anaOutVolts(MAIN_BLOWER_ANA_CH, 0); // set ATD blower speed
anaOutPwr(1); // enable BL2600 power supply to drive D/A o/p
anaInConfig(0, 3); // config A/D channels 0 & 1 for 4-20 mA
anaInConfig(1, 3); // config A/D channels 2 & 3 for 4-20 mA
anaInConfig(2, 0); // config A/D channels 4 & 5 for single-ended unipolar (0-10V)
anaInConfig(3, 0); // config A/D channels 6 & 7 for single-ended unipolar (0-10V)
Still enables the ANALOG OUT for about two seconds before setting to zero VDC.
Suggestions please.
Thanks,
On the BL2600 module, the Power Control Enable/Disable for the DAC analog OpAmp output voltages of +/- 12 V functions as designed, not as desired.
As per the BL2600 schematic, when PWR_CTL is low, NAND U24:A output and therefore both inputs of U24.D are high, leaving Q27 turned on. The result is that the +/-12v outputs do not stay to zero, but starts as two diode drops below +5 and 0v.
Thus the now +5 powered op-amp with 1.667v as a reference and the DAC at zero, the output is pined high at about 2.2v for the 1.25 seconds the module takes from power up till brdInit(); completes. Then when enabled, the DAC power supply functions as required.
This also means that during normal operation, when an anaOutPwr(0); is issued, the op-amp outputs also rest at a nominal +2.25v and power is not OFF, thus not at zero.
As well during a UDPDownload (Network Download Utility) download, as the hardware is held in reset.
Too bad, so sad.
If your design requires a clean start, then an external FET or glass reed (signal level) relay may have to be used. 
Proven concept. Referring to the BL2600 schematic, While PWR_CTL at U24.1 is low, Q27 is left on, resulting in ~ 4 vdc powering the DAC Output Op-Amp. The the Op-Amp outputs go to ~ +2.25v while anaOutPwr(0); Including the nominal 1.5 seconds it takes initializing upon power up.
To mitigate the disturbance, while not an ideal fix, will minimize the voltage pulse to a 100 mS noise burst.
The caveat is that if you add the diode, set anaOutPwr(1); right after Board init(); and do NOT use anaOutPwr(0); as a fault current of near 27 mA Sourced by U24-3 through 100 ohm R78 to the signal sink from U8-14.
The current is tolerated for the power up duration, but NOT steady state.
Cheers…