fast timer with TCLK bit set

The Timer Control registers for the NET+50 have a new bit, the TCLK bit. According to the description, the timer should run with a frequency of [8 * (TC + 1)] / FSYSCLK if the bits are set like this: TCLK = 1 and TPRE = 0. But our timer runs 8-times faster with these settings, at FSYSCLK (44Mhz). Can anyone tell me something about this behavior?

The TPRE bit doesn’t work as stated in the Hardware Reference Manual when the TCLK bit is set to ‘1’. The manual states that when the TCLK bit is set to ‘1’, the timer will divide the SYSCLK by 8 if TPRE is set to ‘0’ and will divide the SYSCLK by 4096 if the TPRE bit is set to ‘1’. The SYSCLK is not divided. The timer counts clock periods. Work Around None needed. The user could use the FXTAL input (TCLK = 0) if they need large timeouts or the SYSCLK input (TCLK = 1) if they need more resolution. Correction The HW manual will be updated to illustrate the increased functionality.