I have the ConnectCore 9C and NetOS 7.5. I have an external RTC and IO Expander both connected to the IRQ2 and IRQ3 lines. I have the GPIO configured to use these inputs as falling edge interrupts. I install two interrupt handlers in the application start function then enable the interrupts. The interrupt routines are really simple, they clear the interrupt register then increment a counter. When I am debugging with the Jtag these function correctly and I can see the counter incrementing. The problem is when I flash the ConnectCore and boot without the debugger we seem to get 1 interrupt then no more. I have tried everything I can think of.
It also looks like maybe the connectcore is driving the IRQ lines low after bootup as I see the IRQ lines go from high to low and stay that way. If I hold down reset the lines stay high and I can make the external chips pull it low. Something in bootup from the flash memory seems to be setting the lines as outputs even though our customized bsp / gpio.c files set them as inputs / irq lines.
The timer interrupts are working, just not external IRQ2 & 3
gpio.h
#define BSP_GPIO_MUX_IRQ_2 BSP_GPIO_MUX_USE_PRIMARY_PATH
#define BSP_GPIO_MUX_IRQ_3 BSP_GPIO_MUX_USE_ALTERNATE_PATH
#define BSP_GPIO_INITIAL_STATE_PIN18 BSP_GPIO_MUX_IRQ_FALLING_EDGE
#define BSP_GPIO_INITIAL_STATE_PIN32 BSP_GPIO_MUX_IRQ_FALLING_EDGE
applicationStart:
printf("Installing RTC IRQ2…
");
result = naIsrInstall(EXTERNAL2_INTERRUPT, (MC_ISR_HANDLER)external_irq2_isr, NULL);
if (result != 0)
{
printf ("NAconfigureGPIOpin failure[%d]
", result);
}
naInterruptEnable(EXTERNAL2_INTERRUPT);
naInterruptEnable(EXTERNAL3_INTERRUPT);
narm_write_reg(NA_SCM_EXTIRQ2_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 1);
narm_write_reg(NA_SCM_EXTIRQ2_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 0);
narm_write_reg(NA_SCM_EXTIRQ3_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 1); narm_write_reg(NA_SCM_EXTIRQ3_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 0);
tx_interrupt_control(TX_INT_ENABLE);
IRQ Function:
//RTC IRQ2
void external_irq2_isr(void * param)
{
/* set the clr bit high in the external IRQ0 register to clear register */
narm_write_reg(NA_SCM_EXTIRQ2_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 1);
/* set the clr bit low in the external IRQ0 register */
narm_write_reg(NA_SCM_EXTIRQ2_REG, NA_SCM_EXTIRQ2_REG_ADDR, clr, 0);
NAsetGPIOpin(LED_RSSI, 1);
isr_int_count2++; /* keep track of interrupts fired */
return;
}