Hi All I’m having some trouble trying to get my startup code to setup the memory controller. I have 8MB of 16bit wide FLASH on CS0 that is setup via boot-strap and 64MB of 32bit wide SDRAM (actually 2 * 16bit wide devices) on CS1. My code then tries to set the following MMU SFR values in this order: MMCR = 0x06800000UL CSOR0 = 0xFF800404UL CSORB0 = 0x00000000UL CSBAR0 = 0x00000003UL CSOR1 = 0xFC000070UL CSORB1 = 0x00000000UL CSBAR1 = 0x0080022DUL I’m expecting this to setup: DRAM refresh = ~8us with a 44MHz clock CS0 -> 000000 - 7FFFFF 16-bit wide 4 wait state FLASH. CS1 -> 800000 - 47FFFFF 32-bit wide CAS2 SDRAM However, one instruction after CSBAR1 is written the Net+50 data aborts… Anyone know what I’m doing wrong? Thanks, Dave PS also the datasheet appears to be very confused about bit 17 of the MMCR register (A25*)… It defaults to 1 but must never be set to 1. Also the description in the new manual appears to have it being the reverse polarity… Anyone know what value is the real safe state for this bit?
The problem is that the Base Address setup of SDRAM on CS1 is not correct. The base address of a chip select must occur on a proper boundary in relation to the peripheral memory size. In your situation, you try to configure 64MB SDRAM, the base address should be 64 MB boundary. If you set base address as 8MB boundary, it will adjust to 0x00000000UL to align with 64 MB boundary and overlap with FLASH on CS0, therefore crash (data abort).
Thanks… it all make sense now…