SDRAM Mode Register

Please, can someone help me to find the address of the “SDRAM Mode Register”? I see the description in item 10.7.8 of the Hardware Reference Guide, but I cannot find the address.

Not sure what you are after… so here are all the memory controller addresses: MEM_BASE = 0xFFC00000UL MMCR = MEM_BASE + 0x00 CSBAR0 = MEM_BASE + 0x10 CSOR0 = MEM_BASE + 0x14 CSORB0 = MEM_BASE + 0x18 CSBAR1 = MEM_BASE + 0x20 CSOR1 = MEM_BASE + 0x24 CSORB1 = MEM_BASE + 0x28 CSBAR2 = MEM_BASE + 0x30 CSOR2 = MEM_BASE + 0x34 CSORB2 = MEM_BASE + 0x38 CSBAR3 = MEM_BASE + 0x40 CSOR3 = MEM_BASE + 0x44 CSORB3 = MEM_BASE + 0x48 MMCR is probably what you are calling the SDRAM mode register… but each CS also has its own config that can effect SDRAM… Regards Dave

I think you are referring to the register that is INSIDE the DRAM chip(s). That register is loaded by the NETARM processor when the V-bit is set in a BAR register preconfigured for SDRAM mode. The configuration bits are transferred using the address bus.

Thank you for your help Dave. Some values I needed to configure in SDRAM are in CSOR. Regards, Rogerio

You are right. This register is inside the DRAM. Now I understand that NET+50 loads this register with the values shown in Hardware Reference Manual, table 10-7. Some values are configured in CSOR and other are hardwired in NET+50. What I do not understand now is why bit9 (Write Burst Mode) is shown to be hardwired to “1” (it means write single mode - no write burst is possible) and Figure 13-13 shows the drawing of a Burst Write Cycle. (There is other question about it posted today: “SDRAM write burst mode”) Thank you for your help, Rogerio.