We have some problems with specific DRAM chips, some other types work fine. We noticed a discrepancy in the SDRAM mode register setup: - The CPU is hardwired to set the SDRAM write burst mode to “single cycle access” (SDRAM.A9 = 1) - In the timingdiagrams, fig 83, there is a drawing of “SDRAM Burst Write” which is illegal if the SDRAM mode is “single cycle”. I’m getting the feeling that the older SDRAMs ignored this bit, but the newer chips do look at it… We do use burst mode writes (multiple register stores). What is the real mode of the SDRAM write, burst or single cycle? Regards, Arie de Muynck
The NET+50 can execute a burst write transfer to an SDRAM device which has been set to except single cycle transfers. It does this by incrementing the address on each clock cycle. Technically it is executing sequential single cycle writes, but because the writes are on sequential clocks it really is bursting from the standpoint of the 50. A burst of 4 will follow this sequence for 6 clock cycles, (precharge) (active) (write) (write) (write) (write), it works.