The schematics of the evaluation board in the Jumpers and Components Guide refer to an “SDRAM workaround”. What is being worked around, and do I need the workaround in my design?
When the NET+ARM experiences a hardware-reset condition, the SDRAM controller might be in the middle of a Burst Read condition. The hardware-reset stops the memory controller preventing the NET+ARM from issuing the BURSTSTOP command to the SDRAM. This condition leaves the SDRAM components in a state where they will forever drive the data bus. This prevents the NET+ARM from being able to reboot from CS0 since a data bus clash will be found on the system bus while attempting to read from the CS0 boot device. The workarounds for this issue are briefly described in details in the errata.
I have some questions to the SDRAM workaround: 1.) power up As long as I don’t have a stable power supply, I think that the AND-gates can not have a determined value. Do the GPIO of the NetARM and the other control signals also toggle, if the power supply is rising slowly? In this case the SDRAM may see any command at start up. Is this a problem? 2.) timing For the SDRAM burst termination patch a Fairchild NC7SZ08_SOT23 AND-Gate is used in the errata for the CS and the CAS1. The Datasheet for the NetARM50 (P/N: 8820002A Release date: August 2002) says “BCLK high to CS* valid” needs up to 16 ns. According to the Datasheet of Fairchild, this Gate has a maximum Propagation Delay of 5.0 ns (@3,3V). The Datasheets for different SDRAMs define a minimal setup-time of 2ns. So The BCLK has to be at least 16ns + 5ns + 2ns = 23ns. But it is only 22.6ns @ 44.2368MHz. Is this calculation correct? Do we have to use much faster Gates in order to get a stable system?
I am checking the question you raised. Will update you shortly.
The AND gates are “simple logic” and will be stable long before the SDRAM “complex logic” is. The NETARM chip selects will drive up to a logic “1” following the ramp up of VCC. There will be no BCLK until the crystal cranks up. Some crystals take as long as 10MS. As for timing; The calculation is correct, but one should consider that the 16ns is based on worst case temperature, voltage, and ASIC process, + 25pF loading. In the real world all of these conditions would not likely exist at the same time. The existing SDRAM BT Work-A-Round circuit was based on the previous HRG in which t40 = 12.5ns. For those who need to meet the latest worst case timing under all conditions, I suggest the attached updated SDRAM Work-A- round
Any reason a fix can’t look like the attached?