Hello everybody we are interfacing SDRAM(IS42S16400B) to the MPC860p. i have changed the configuration file according to the taget boad(custom Board).SDRAM is not getting initialised can any body what is wrong with the configuration.plese find attached configuration. ; bdiWind configuration file for MPC860Costom board ; ---------------------------------------------- ; ;custom Board [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI WSPR 27 0x00001002 ;SRR1 : ME,RI WSPR 149 0xFFE7400F ;DER : set debug enable register ;WSPR 149 0x0082000F ;DER : enable PRIE,TRE,LBRK,IBRK,EBRK,DPI WSPR 638 0xFF000000 ;IMMR : internal memory at 0xFF000000 for custom board WSPR 158 0x00000007 ;ICTRL : ; init SIU register WM32 0xFF000000 0x00610440 ;changed the value of SIUMCR by prabhu on 13/03 WM32 0xFF000004 0xFFFFFF88 ;SYPCR ;WM16 0xFF000200 0x0002 ;TBSCR ;WM32 0xFF000320 0x55CCAA33 ;RTCSCK: unlock real-time clock status and control register ;WM16 0xFF000220 0x0102 ;RTCSC ;WM16 0xFF000240 0x0002 ;PTSCR WM32 0xFF000384 0x55CCAA33 ;PLPRCRK: unlock PLL register WM32 0xFF000284 0x00104000 ;PLPRCR set clock to 80MHz ; init UPM SUPM 0xff000168 0xff00017c ;MCR and MDR Address Reprogrammed Here ;UPMA RAM Array ;UPMA single read WUPM 0x00000000 0x0f07fc04 ; ACTIVE WUPM 0x00000001 0x0ffffc04 ; NOP WUPM 0x00000002 0x00bdfc04 ; READ WUPM 0x00000003 0x00fffc00 ; NOP WUPM 0x00000004 0x0ff77c00 ; Refersh Cycle change on 17 /03 / 04 0x0ff77c00 WUPM 0x00000005 0x1ffffc05 ; last ( NOP ) WUPM 0x00000006 0x1ff7fc05 ; Precharge with last bit WUPM 0x00000007 0xefaabcf5 ; Initializing MODE Refister Set up and last bit ;UPMA burst read WUPM 0x00000008 0x0f07fc04 ; ACTIVE WUPM 0x00000009 0x0ffffc04 ; NOP WUPM 0x0000000A 0x00bdfc04 ; READ WUPM 0x0000000B 0x00fffc00 ; NOP WUPM 0x0000000C 0x00fffc00 ; NOP WUPM 0x0000000D 0x00fffc00 ; NOP WUPM 0x0000000E 0x0ff77c00 ;Refersh Cycle change on 17 /03 / 04 0x0ff77c00 WUPM 0x0000000F 0x1ffffc05 ;last ( NOP ) WUPM 0x00000010 0xFFFFCC25 WUPM 0x00000011 0xFFFFCC25 WUPM 0x00000012 0xFFFFCC25 WUPM 0x00000013 0xFFFFCC25 WUPM 0x00000014 0xFFFFCC25 WUPM 0x00000015 0x00fffc00 ; NOP Loop starts here WUPM 0x00000016 0x00fffc00 ; NOP WUPM 0x00000017 0x00fffc05 ; last ( NOP ) ;UPMA single write WUPM 0x00000018 0x0f07fc04 ; ACTIVE WUPM 0x00000019 0x0ffffc00 ; NOP WUPM 0x0000001A 0x00bd7c04 ; WRITE WUPM 0x0000001B 0x0ffffc04 ; NOP WUPM 0x0000001C 0x0ff77c04 ; Refersh Cycle change on 17 /03 / 04 0x0ff77c00 WUPM 0x0000001D 0x1ffffc05 ; last ( NOP ) WUPM 0x0000001E 0xFFFFCC25 WUPM 0x0000001F 0xFFFFCC25 ;UPMA burst write WUPM 0x00000020 0x0f07fc04 ; ACTIVE WUPM 0x00000021 0x0ffffc00 ; NOP WUPM 0x00000022 0x00bd7c00 ; WRITE WUPM 0x00000023 0x00fffc00 ; NOP WUPM 0x00000024 0x00fffc00 ; NOP WUPM 0x00000025 0x00fffc04 ; NOP WUPM 0x00000026 0x00fffc04 ; NOP WUPM 0x00000027 0x0ff77c04 ;Refersh Cycle change on 17 /03 / 04 0x0ff77c00 WUPM 0x00000028 0x1ffffc05 ;last ( NOP ) WUPM 0x00000029 0xFFFFCC25 WUPM 0x0000002A 0xFFFFCC25 WUPM 0x0000002B 0xFFFFCC25 WUPM 0x0000002C 0xFFFFCC25 WUPM 0x0000002D 0xFFFFCC25 WUPM 0x0000002E 0xFFFFCC25 WUPM 0x0000002F 0xFFFFCC25 ;UPMA refresh WUPM 0x00000030 0x0ff77c04 ; PRECHARGE ALL ;Refersh Cycle change on 17 /03 / 04 0x0ff77c00 WUPM 0x00000031 0x0ffffc04 ; NOP WUPM 0x00000032 0x0ff5fc84 ; AUTO REFRESH WUPM 0x00000033 0x0ffffc04 ; NOP WUPM 0x00000034 0x0ffffc04 ; NOP WUPM 0x00000035 0x0ffffc84 ; NOP WUPM 0x00000036 0x1ffffc05 ; last ( NOP ) WUPM 0x00000037 0x0FF74C35 WUPM 0x00000038 0x0FFACCB5 WUPM 0x00000039 0x0FF5CC35 WUPM 0x0000003A 0x0FFFCC35 WUPM 0x0000003B 0x0FFFCCB5 WUPM 0x0000003C 0xfffffc04 ;UPMA exception WUPM 0x0000003D 0xfffffc04 WUPM 0x0000003E 0xfffffc04 WUPM 0x0000003F 0xfffffc05 ;last WM32 0xFF000170 0x27802444 ; MAMR Register WM16 0xFF00017A 0x0200 ; MPTPR : divide by 32 ; init memory controller WM32 0xFF000100 0xFF800001 ;BR0 base address FF800 , 32 bit port size , WM32 0xFF000104 0xFF800930 ;OR0 8MB FLASH all accesses, CS early negate, 6ws, time relax WM32 0xFF00010C 0xFF000800 ; OR1 16MB SDRAM WM32 0xFF000108 0x00000081 ; BR1 base address 0x00000,32 bit port size,UPMA machine ; controller starts Here Additional initialization ;SUPM 0xFF000168 0x80002015 ; NOP command for delay ;SUPM 0xFF000168 0x80002006 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ; Precharge and mode register value ;WM32 0xFF000164 0x000000c8 ; MAR Value to be loaded into mode register( leftshift twice ) ;SUPM 0xFF000168 0x80002030 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ; Address multiplex size=0x000, 1-cycle disable period, General line 0 control=A11 ; Auto Refresh command ;SUPM 0xFF000168 0x80002007 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ; Precharge and mode register value ( MSR Value ) ; end of controll sdram ; controller starts Here Additional initialization SUPM 0xFF000168 0x80002006 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ; Precharge and mode register value WM32 0xFF000164 0x00000088 ; MAR Value to be loaded into mode register( leftshift twice ) WM32 0xFF000168 0x80002007 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ; Precharge and mode register value WM32 0xFF000170 0x27802448 ; MAMR : periodic timer A period = 0x39 , periodic timer A enabled , SUPM 0xFF000168 0x80002030 ; MCR and RUN command chip select=1,UPMA machine,memory command loop=0000(16 times) MAD=5; ;Address multiplex size=0x000, 1-cycle disable period, General line 0 control=A11 ; Auto Refresh command WM32 0xFF000170 0x39802444 ; MAMR : periodic timer A period = 0x39 , periodic timer A enabled , origial MAMR WM32 0xFF00010C 0xFF000800 ;OR1 16MB SDRAM WM32 0xFF000108 0x00000081 ;BR1 base address 0x00000,32 bit port size,UPMA machine ; end of controll sdram [TARGET] CPUCLOCK 80000000 ;the CPU clock rate after processing the init list BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoints ;STEPMODE HWBP ;TRACE or HWBP, HWPB uses one or two hardware breakpoints ;STARTUP STOP 5000 ;let the monitor initialize the system ;DCACHE FLUSH ;flush data cache, needs a workspace of 32 bytes ;WORKSPACE 0x00000040 ;workspace in target RAM for data cache flush ;MMU XLAT ;translate effective to physical address ;REGLIST SPR ;select register to transfer to GDB REGLIST ALL ;select register to transfer to GDB [HOST] IP 192.168.1.39 ;FILE E:\cygwin\home\bdidemo\mpc860\vxworks FILE u-boot.bin FORMAT BIN 0x00000000 LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 ;DUMP C: emp\dump.bin [FLASH] CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x200000 ;The size of one flash chip in bytes (e.g. AM29LV160DB = 0x200000) ;WORKSPACE 0x02202000 ;workspace in target DPRAM BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin ;The file to program FORMAT BIN 0xFF800000 ; ERASE 0xFF800000 CHIP ;chip erase flash SIMM ; ERASE 0xFF800000 ;erase sector 0 of flash SIMM 16Kbyte ERASE 0xFF804000 ;erase sector 1 of flash SIMM 8 Kbyte ERASE 0xFF806000 ;erase sector 2 of flash SIMM 8 kbyte ERASE 0xFF808000 ;erase sector 3 of flash SIMM 32 kbyte ERASE 0xFF810000 ;erase sector 4 of flash SIMM 64 kbyte ERASE 0xFF820000 ;erase sector 5 of flash SIMM 64 kbyte ERASE 0xFF830000 ;erase sector 6 of flash SIMM 64 kbyte ERASE 0xFF840000 ;erase sector 7 of flash SIMM 64 kbyte ERASE 0xFF850000 ERASE 0xFF860000 ERASE 0xFF870000 ERASE 0xFF880000 ERASE 0xFF890000 ERASE 0xFF8a0000 ERASE 0xFF8b0000 ERASE 0xFF8c0000 ERASE 0xFF8d0000 ERASE 0xFF8e0000 ERASE 0xFF8f0000 ERASE 0xFF900000 ERASE 0xFF910000 ERASE 0xFF920000 ERASE 0xFF930000 ERASE 0xFF940000 ERASE 0xFF950000 ERASE 0xFF960000 ERASE 0xFF970000 ERASE 0xFF980000 ERASE 0xFF990000 ERASE 0xFF9a0000 ERASE 0xFF9b0000 [REGS] DMM1 0xFF000000 FILE reg860.def
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