Hi
I have a question concerning the max. I/O speed that can be achieved with the RCM3700 module. Currently I achieve a data rate at one I/O ports of approx. 500 kbits. Can I make this faster?
Hi
I have a question concerning the max. I/O speed that can be achieved with the RCM3700 module. Currently I achieve a data rate at one I/O ports of approx. 500 kbits. Can I make this faster?
Hello jk,
I answered the following to Baja in a post named “MAX I/O speed (RCM7000)?” (I copied and pasted because I didn�t know how to post only the link, sorry)
"Hello Baja,
Trying to find out how much time it takes to my Rabbit 3000 uP (@29Mhz) I ran the following code:
/****************************************************/
#class auto
#no debug
main()
{
useMainOsc();
clockDoublerOn();
WrPortI(PCFR,&PCFRShadow,0); /*Port C setup*/
WrPortI(PCDR,&PCDRShadow,0x08); /*pin 4: High*/
while(1) /Infinite loop
{
BitWrPortI(PCDR,&PCDRShadow,0,4);
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4); / Repeats the instruction to avoid the delay of executing the while loop*/
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4);
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4);
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4);
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4);
BitWrPortI(PCDR,&PCDRShadow,1,4);
BitWrPortI(PCDR,&PCDRShadow,0,4);
}
}
With this code I measured the time between the 0 to 1 transition to the next 1 to 0 and it took 1.4useg.
The key word is the #no debug directive that tells the compiler not to introduce an interrupt after every C line to allow Dynamic C to debug the code (Remember that when you are conected via the programming port the uP is permanently being polled).
Another thing, you have to download this program to flash and unplug the programming cable to allow the uP to run stand alone at full speed. If you forget the programming cable connected a message telling you that Dynamic C lost connection with the host will appear (that�s because as the uP is not interrupted it can�t be polled).
Hope this will help you. If you have a better idea please let me know (I am also new at this)
Luciano
PS: just to compare. A workmate downloaded to FPGA from Xilinx (Spartan 3) a uP core from xilinx named Microblaze and ran the same experiment with a 50Mhz clock. Well, It took 1usec to the FPGA to do the same so I think that the rabbit runs."
As you can see the RCM3000 access to the world at 714kHz so I think you can do better with the RCM7000.
Regards
Luciano