I am having problems with RTS hardware handshake. During initialization I set the RTSRX bit in CRA. (RTSTX in CRB is not set and it doesn’t seem to make any difference if RTS in CRA is set.) Now when I send >=32 bytes to the NS7520 while not reading anything from the FIFO, I would expect the RTS line to go inactive (high) after 28 bytes. But it remains active and the FIFO overruns. Am I doing something wrong or is this a hardware bug?
Serial Driver Update: This version fixed packet delay and data loss at high baud rates with HW and SW flow control. When lots of data comes to the board which is in initialization stage, then packet delay and data loss is observed. The reason is that the interrupt handler read data from receive FIFO and put data into receive buffer and make the buffer almost full to reach the threshold and disable interrupt, thus some data is still in FIFO and results in packet delay. If more data >32 bytes coming before other side stops sending, data loss occurs. The second reason is that the interrupt handler reads data from receive FIFO and does not put in receive buffer and results in data loss. The third reason is that the interrupt handler reads status register at beginning and then always use this data to receive side state, resulting packet delay or data loss. Solutions: 1. Decrease receive buffer threshold. 2. When reach the threshold, not disable interrupt but decrease RTS. 3. Continue to read data after reach the threshold and put in receive buffer. 4. Read data from FIFO data register only after reading data length from status register. 5. Always using the current status register value to check receive side state. Make sure that you rebuild the bsp prior to building any of your applications and let us know of your results.