Having some difficulty here getting reliable results.
Using port B, PB0 (clock), PC4-PC5 MOSI/MISO, chip select logic done using PortA. Using Slave ready logic.
So I get the stuff to work. A simple program on the RCM4110 (master) sending 4 bytes, the RCM4010 (slave) flips them around and sends them back. No brainer. Works for a few packets and at some point the slave gets stuck in trying to send the byte. Looks like the master is 1 clock cycle ahead or so. Since the master believes it received all the data, it no longer sends a clock signal, the slave is waiting to finish sending a byte, and never finishes, the master is waiting for the slave to release the ready signal, which it never does because of the missed clock signal.
I have played with clock phase, clock divisor, and always the same result. The slave is at some point stuck in a state where it is still trying to send some bits but the clock has gone away.
Has anyone been able to get this to work reliably? Without the slave ready logic to slow down the whole process, the 2 modules get out of sync so fast it’s not funny.
Any previous experience in clocked serial ports for the 4xx0 modules would be greatly appreciated.