UART FIFO registers?

Hi All Does anyone know how these SFRs work with respect to endianess and transmission/reception order? I’m assuming in little endian mode the byte at the lowest address is the first received when reading the register and the first sent when writing to the register… and in big endian mode the first Rx/Tx byte is at the highest address… However, I can’t appear to find any info on the subject in the manual/data sheet… Thanks, Dave

The manual appears to detail the operation for SPI mode but not interrupt driven UART mode… Does anyone no if its the same? Thanks Dave

Unfortunately NetArm does not allow setting endianess for the individual pereferials and their behaviour is determined by the endianess of the system

When I originally said “Endian mode” I was referring to the ARM cores current operating mode… my question was basically: 1) which byte is first out when writing to the FIFO with the core in big endian mode and with the core in Little endian mode?.. The spec details that its the lowest address byte in both endian modes for SPI mode… but is it the same in UART mode? 2) Ditto for reading from the FIFO. Regards, Dave