Using FIQ with NET+50 CPU

We should know which sources can fire the fast interrupt and how it is to configure. Unfortunately we haven’t found any document in which it is described exactly. To solve our problem we have to fire FIQ with DMA controller.

Hi Chris The FIQ can only be used with the two counter/timers… and the watchdog… all the other sources use the standard IRQ Regards, Dave

This app note may also be of some use:

Thank you for your answer! We have suspected this. Unfortunately this makes us some timing problems! Can you give us any hints where to find information about normal interrupts (latency)?

Hi Chris For info on basic interrupt latency I’d look on the ARM website as they have some good reference manuals for exceptions… From memory I think both the IRQ and FIQ are about the same basic latency for the context switch its just the FIQ entry being the last in the vector table allows its handler code to begin from that address without a branch… and the FIQ has more alternate register available… Mostly the latency will depend on what opsystem you are using… and this generic IRQ support can sometimes be improved by moving the “case” for your interrupt source further up the switch statement in the main IRQ handler… and to further improve things you can move your IRQ sub-handler code inline as well… which will save an additional level of branch and register push… … never have liked the ARM architecture when it comes to IRQ support… which Netsilicon’s limited use of the FIQ line hasn’t improved… And some compilers don’t help the situation with there IRQ support… for example GCC doesn’t make nearly enough use (if any) of the alternate registers available in IRQ and FIQ modes… resulting in additional register push and pop overhead. BBFN Dave