Using UART with CGAP Timer and RIE_CLOSED

Hello,I am trying to create a serial driver that uses the CGAP timer and half full interrupt mode to reduce the number of interrupts generated. To do this I set the interrupt enable bits to NS_SER_CTRL_A_RIE_HALF | NS_SER_CTRL_A_RIE_CLOSED Set the bit NS_SER_CTRL_B_RCGT I also initialise the CGAP timer to 1 character period and set the NS_SER_RX_CHAR_TIMER_TRUN bit However the RIE_CLOSED interrupt is never being triggered. When the following data arrives : <1 garbage byte>, <2 second delay>, <88 byte data frame #1>, <2 second delay>, <88 byte data frame #2>, <2 second delay>, <88 byte data frame #3> This is received as follows: Interrupt 1: Garbage byte + 12 data bytes from frame1 (RBC is true after reading one byte) [normal] Interrupts 2-5: 16 data bytes each from frame 1 Interrupt 6: 12 data bytes from frame 1 (RBC is true after reading last byte) [normal] Frame 1 is thus correctly received Interrupt 7 - 11: 16 data bytes each from frame 2 There are still 8 bytes of frame 2 to be received but no more interrupts occur until frame 3 is sent At which point : Interrupt 12: Last 8 bytes of frame 2 and first 4 of frame 3 (RBC is true after reading 8 bytes) Interrupt 13 - 17 16 data bytes each from frame 3 Upon entry to the ISR RHALF is always true, RBC is always false and RBCPEND is always false except for the first interrupt. My interpretation of this is that the CGAP timer is working (as the RBC bit is positionned at the correct point when reading the buffer) but that no interrupt is being generated for some reason. Hence data is only read when RHALF is true. If I use NS_SER_CTRL_A_RIE_RDY instead of NS_SER_CTRL_A_RIE_HALF the behaviour is correct (no truncated frames) but there is then 1 interrupt every 4 bytes (too many)! This is with a NS9360 (I have seen the errata regarding the serial ports but they only apply to the NS9750?). Does anyone have any ideas about this? Regards, Martin

UART Gap Timer Erratum Rev 1.1 10-26-2005 Overview: The start bit of a new character may not be detected when the character or buffer gap timer expires. Framing, parity, or data corruption occur when a start bit is missed. Chips affected: NS9775, NS9750B-0, NS9750B-A1, NS9360 Software Workaround: There are several software workarounds for this erratum. 1. Applications with a steady stream of receive data are not affected if the buffer gap timer is disabled. 2. Applications where the gap between characters is fixed and the character gap timer period is configured to be less than the fixed period. The buffer gap timer must be disabled. 3. Applications that have higher-level protocol error detection and recovery such as PPP can use both the buffer and character gap timers. Hardware Workaround: A hardware workaround has been devised to eliminate the possibility of receiving a start bit when a character or buffer gap timer is expiring. The workaround drives the baud clock off-chip and synchronizes the incoming data with this clock. By doing so, the buffer and character gap timers and the next start bit will have a fixed and known relationship with each other. The workaround is applicable to all affected chips. Limitations: 1. The TMODE bit in the Bit-rate register must be cleared. 2. Baud rates are limited to those available in x16 mode. 3. Baud rates with a divisor of 0 are not possible for all CPU frequencies. This translates to a max baud rate of 460k in x16 mode. 4. Baud rates with a divisor of 1 are not possible for CPU frequencies below 147MHz. This translates to a max baud rate of 230k in x16 mode. 5. The buffer and character gap timers must be an even multiple of the sample clock period. For a 9600bps UART in x16 UART mode, the equation is as follows: Timer increment = ((1/9600) / 16) x 2 = 13.020us 6. One GPIO per UART is required to output the baud clock. The baud clock can be output on the RI pin on each UART. This function is controlled by the RXEXT bit (27) in each Serial Bit-rate register. 7. If multiple UARTs are running the same baud rate, then one baud clock can be used for the multiple UARTs. Workaround Details: A drawing for this workaround can be obtained by submitting a request via the report web page.