There are an example on how to manage the watch-dog? According to the manual, i’ve set the register: (*NCC_GEN).scr.bits.swt = 3; (*NCC_GEN).scr.bits.swri = 2; (*NCC_GEN).scr.bits.swe = 1; then with a timer I write (*NCC_GEN).swsr.bits.swsr = 0x5a; (*NCC_GEN).swsr.bits.swsr = 0xa5; every 100 msec. But the sistem halt (and do not restart!) Any suggestion?
What you see doesn’t surprise me since to the best of my knowledge, the board designers and end users that plan to use NET+40-4 and NET+50-1 have to avoid the watchdog timer problem - the problem that you ended up seeing where the board hangs after reset. To have a watchdog timer work reliably the design must either: a. Use an external oscillator (PLL disabled). Here you need an SDRAM work-a-round which requires 7 gates (OR, 2 ANDs, EXOR, and 3 NANDs). b. Use an EXTERNAL Watchdog IC (PLL enabled). Here you need an SDRAM work-a-round which requires 3 gates (OR and 2 ANDs).