watchdog retrigger

Hello,i want to use the internal watchdog, but i find no description how the watchdog has to be retriggered after he is once started. Can anyone give me a hint ? Besides i had read anywhere :-(unfortunately i dont know where :slight_smile: that there were problems with internal watchdog. Does anyone konw about that ? Martin

In order to retrigger watchdog, please write $5A and $A5 into Software Service Register ( 0xFFB0 000C) using two separate write operations.

To the best of my knowledge, the board designers and end users that plan to use NET+40-4 and NET+50-1 have to avoid the watchdog timer problem. To have a watchdog timer work reliably the design must either: a. Use an external oscillator (PLL disabled). Here you need an SDRAM work-a-round which requires 7 gates (OR, 2 ANDs, EXOR, and 3 NANDs). b. Use an EXTERNAL Watchdog IC (PLL enabled). Here you need an SDRAM work-a-round which requires 3 gates (OR and 2 ANDs). These work-a-rounds are the described briefly in the NET+50 errata that could be found on teh Netsilicon web site. Bottom line is that the 50-1 will require an external oscillator or an external watchdog IC for the watch dog RESET timer to work reliably, The 50-3 has corrected this.