Just in case anyone comes across the same problem as us: If you follow the NetSilicon guide (Dec '01) that states the PLL is safe to use over a temperature of 0-85C, you will find that the chip reliably starts and runs normally, but if a watchdog reset ever occurs, the PLL may fail, resulting in a locked up Net50. This happens because the Net50 is not providing time for the PLL to stabilise after a watchdog reset, so the PLL can generate a frequency higher than 44MHz after the very short reset time, resulting in Net50 lockup. The only way I know of to guarantee reliable operation of a Net50 is to use an external oscillator module.
An oscillator is fine or you can stick with the Xstal provided you implement some sort of external watchdog and write a routine to bang it from SW. Do not put the routine in an ISR though - NETsilicon has done that for the SW watchdog and I think that is bad design.
There is an old errata (“Watch-dog timer reset can cause CPU to hang”) which says: Two workarounds are available, both equally effective: Use an external watch-dog timer Use an external oscillator and proceeds to give details of each. But, this is fixed on the new version of the NET+50, and the old Watch Dog Timer errata is no longer posted on the website.
The board designers and end users that plan to use NET+40-4 and NET+50-1 have to avoid the watchdog timer problem. To have a watchdog timer work reliably the design must either: a. Use an external oscillator (PLL disabled). Here you need an SDRAM work-a-round which requires 7 gates (OR, 2 ANDs, EXOR, and 3 NANDs). b. Use an EXTERNAL Watchdog IC (PLL enabled). Here you need an SDRAM work-a-round which requires 3 gates (OR and 2 ANDs).
What amazes me is that I just downloaded the errata sheet for the NET+50 (NET50_3_Errata_8833414B.pdf) and there is no mention this in the datasheet. Why would you remove it if there is still stock circulating?
Because it is fixed with 50-3!
I just checked our inventory and all my NET+50’s are marked 57504B/0136991 which implies I have an early version of the silicon.