Chip internal RESET logic

Hello NetSilicon-Hackers … I have problem in understanding the reset logic. How to reset the CPU in hardware and software ? What does the 5A + A5 to the software service register ? Only retrigger of watchdog supervision or more ? What does the 123 + 321 to the same register. A software reset ? But why executes the CPU further instructions ? Or does it only reset the peripheral parts ? Which one ? Is there a better docu the the NS7520 HR I have, explainig the reset logic (in all aspects) not only describing the registers. Bye Christoph P. (Please also mail to

Reset through Software Service Register ( 0xFFB0 000C) by writing 123 and 321 is not software reset, it actually is a partial hardware reset (reset all devices except CPU and memory module), therefore, the cpu continue to execute the command immediately following the writing 123 and 321 reset command. For NETOS V5.1, we have a function for software reset. You can call blExecuteImage(Reset_Handler_ROM). It is in blExe.s file in bsp.a library. Watchdog timer reset is totally hardware reset. Writing 5A and A5 to the Software Service Register before its timeout reinitializes the watchdog timer, avoiding watchdog timeout for reset or generating interrupt depending on your configuration of watchdog.