Do I need to add bus transceivers to my design?
I notice that on page 266 of the NS7520 HW Reference Rev. c, there is a Figure 30 “System Configuration for Specified Timing” showing 2 SDRAMS and 1 buffer connected to each pin.
Without adding bus transceivers, are any more devices allowed? Is so, how many before the system malfunctions?
I don’t have a CPLD, but I have 2 SDRAMS and two flash chips like on the dev board plus an 8-bit Dual-Port RAM. Can I get away without adding bus transceivers and associated glue logic? I’m only 1 or 2 parts greater than the table indicates.
Any help is greatly appreciated!!!
Got a reply from Digi so I’m posting here for everyone’s benefit…
At 55MHz bus speed and 5 inch traces, the Memory bus can drive three loads without use of buffers.
No Local trace length should exceed 5 inches (127mm).
The three load limit must be complied with to operate at 55MHz over worst case Voltage, Temperature and ASIC process.
With shorter traces and slower bus speeds more loads may be possible. Each inch of trace adds 180pS based on 3.3pF per/inch.
In your description I count three loads on the data bus and 5 on some of the address lines.
This assumes that the 2 SDRAM and Flash IC’s are x16 parts to makeup a x32 bit data bus.
Device Address Data
2 SDRAM 2 1
2 Flash 2 1
1 Dp RAM 1 1
In order to operate at the worst case conditions, the address lines need to be connected directly to the SDRAM’s, then those that are used for flash and the DP ram need to be passed through an address buffer. One wait state would need to be added to these chip selects.
I hope that this helps.
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