CS3 as external Asyn SRAM but data is wrong

Dear sir, we use cs3 to select a fpga and read write data from it. it is O.K. when use NETARM 40 but read will wrong when use NETARM 50.After that I use the Logic Analyzer find the data on the bus is correct when cs3 is low.why the same software got the different data ? regards,

Are you running the NA50 at 44Mhz? Did you increase the wait states? Do you use the external TA signal? If yes, try to set the stage synchronizer. The timing of the NA50 is worse than the timing of the NA40. Did you check setup and hold times?

voma,Thanks for your reply,I make a mistake on memory map. cs3 overlap cs2.So that situation will happen.But it is insteresting the data bus show the right data the register get the wrong data?

That’s interesting. Did you also use the wrong software on the NA40 and it worked? Btw did the NA50 use the timing for CS2 or CS3?

On the NA40 the mmap is right. and On the NA50 using wrong mmap,the timming will use CS2’s setting.