Net+50 SRAM timings?

The 88334850A NET+50 manual describes the chip select option register RSYNC/WSYNC bits as selecting synchronous read/write timings for a chipselect when set… However, the description says OE*/WE* active low inside the CSx* active low period… but the sync SRAM timing diagrams have CSx* active low inside the OE*/WE* active low periods? So what setting for the RSYNC/WSYNC bits do I actually need to have the cycle timing shown in the Sync SRAM timing diagrams of Figures 61/62 (pages 427 - 428)?

BTW sorry for posting the same message on both the NET+50 and documentation lists… This is technically a documentation screw up… but thinking about it my answer is more likely to come from the Net+50 list… Regards, Dave

What not replies? I’ll guess I’ll have to suck-it-and-see with a scope monitoring the chip select and control lines :frowning: