The 88334850A NET+50 manual describes the chip select option register RSYNC/WSYNC bits as selecting synchronous read/write timings for a chipselect when set… However, the description says OE*/WE* active low inside the CSx* active low period… but the sync SRAM timing diagrams have CSx* active low inside the OE*/WE* active low periods? So what setting for the RSYNC/WSYNC bits do I actually need to have the cycle timing shown in the Sync SRAM timing diagrams of Figures 61/62 (pages 427 - 428)?
The Net+50, i believe, is not supported - but the setting would depend upon the requirements of the SRAM - the chip can accommodate either. History has wr/rd inside cs