Hi,I have tried to use the busy signal from a dual port RAM to delay the Net access at DPRAM address matches via the TA input. The problem is that for normal accesses the TA signal will not be pulsed but low all the time. Looking at the asynchronous SRAM timing diagrams it seems as Net will sample the TA signal after the wait state periods. It also says that TW cycles will be present when WAIT is set to 2 or more. We have tried to insert wait states for the CS but the DPRAM access will still only be 88 ns, i.e two periods when TA is enabled. This indicates that Net samples TA immediately after the T1 period. If this is the case, during an address match the cycle will be terminated before TA is sampled by the Net as it needs to be synchronised. We have also tried to use synchronous mode with the same results. Is this the correct function of the SRAM access? If so, I suppose we need to generate a pulsed TA signal to terminate or hold the access.
The lack of wait states was due to the busy bit being low most of the time. You would not be able to drive TA hi soon enough (16 ns delay of CS and 8ns set up for TA. Therefore you must keep TA high most of the time, pulse it low at the appropriate time for most transfers, and delay the low pulse when busy is high.