The ENI interface

I intend to connect a PLX9030 PCI slave to the ENI interface for accessing a part of the SDRAM via the PCI-bus. I suppose I then have to use the PACK* signal to hold the access cycle while NET+50 accesses the SDRAM. I noticed in the errata that the PACK* could be stuck at active low. It says that it is a random failure, but in the workaround it seems as it is connected to the PCS* synchronization. Is this correct and does the workaround fix the problem?

Yes it does!

Is the dual rank flip-flop needed if the PLX circuit is clocked by the BCLK of NET+50 and thus synchronous with it?