code size for flash & async SRAM operation

Hi , I have two questions here , 1. I understand that NS7250 can execute 32-bit standard ARM set and 16-bit thumb set. If I just use 1pc 16-bit boot Flash(locates in CS0)and 1pc 16-bit SDRAM , can I generate 32-bit standard ARM set code , and run it in this 16-bit flash. if can , it means that CPU need to fetch code twice per instruction-cycle. 2. if configure CS0 to SRAM operation mode , it can be worked in sync mode , or async mode . can you tell me how to configure it ? any register or any initialization strap setting for this? thanks,

There are two concepts here - the first is the difference from “THUMB” mode and “ARM” mode - and the second is the difference from 16-bit SDRAM databus and the 32-bit SDRAM databus.