Hi,I am trying to write a ISR for external interrupt on NS9750 specifically for a touchscreen PENIRQ singal but so far with no success. First, I set gpio 13 to function 1 (EXT IRQ 0 duplicate). Then I set LVEDG, CLR and PLTY in External Interrupt Control Register. Next, I enable the interrupts by setting IE in Interrupt Config Register 28. Finally, request_irq is called. My interrupt handler at the moment is just a printk(). Can anyone point out what I’m doing wrong?? I ’ attaching the source code below. Thanks in advance, Terence Soh >>>>>>>>>>>>>>snip<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< request_gpio( 13, 1, DRIVER_NAME); set_gpio_cfg( 13, NS_GPIO_CFG_FUNC_1 ); /* External Interrupt Control Register Configuration / writel( NS_SYS_EXT_INT_CTRL_LVEDG | NS_SYS_EXT_INT_CTRL_CLR | NS_SYS_EXT_INT_CTRL_PLTY, NS_SYS_EXT_INT_CTRL(0) ); / Interrupt Configuration Registers / i = readl(NS_SYS_INT_CFG_BASE + 28); i &= 0x1FFFFFFF; i |= 0x80000000; writel(i,NS_SYS_INT_CFG_BASE + 28); / Request IRQ for IRQ0 interrupt */ if ( request_irq( IRQ_EXT_0, ns_ts_irq_int, 0, DRIVER_NAME, 0) ){ printk("ns9750ts_input.c: Could not allocate External IRQ0!
"); return -EIO; } >>>>>>>>>>>>>>snip<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
Hi,Which Linux port are you using ? The one from FS-Forth ? Did you check that external interrupts are decoded in arch/arm/ns9750/irq.c ? Does this Linux-Port programm the Interruptcontroller to 1:1 Mapping between Source IRQ’s and Interrupt Levels ? Jochen
Thanks for your reply. I’m using the linux port from FSForth. Managed to get the irq_handler to respond at active low. It is still a bit weird though. When interrupt is configured to trigger at falling or rising edge, irq_handler is always called even when there isn’t any edges on the signal. Will leave it alone for now and look at it again later… Is your linux port for the NS9750 evaluation board or your own board? Thanks, Terence Soh.
Hi,>Is your linux port for the NS9750 evaluation board or your own board? My Linux works on our board and on the development board. Booting currntly works without U-boot. So you need to do memory controller settings in kernel header. Next version of my emulator will have a clean support of multiple boards, and maybe one year it will have a check of DRAM Timings. Jochen
Hi,More questions about your booting. Are you booting from the 8MB flash or the SPI EEPROM. If you are booting from the EEPROM, is there any help avaliable either from NetSilicon or yourself(that is if it is open-source)? Thanks again, Terence Soh