I am trying to connect an Xbee S6 to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the correct output when I try to implement it. I connected dout from the Xbee to ground to initiate SPI mode, but i’m not sure how to confirm this. I have my clock set to 20 Mhz and the clock divider sets the SPI clock to under 5Mhz. Also, if I am just using one slave, can my select (ss) be held to zero?
I have a remote PC with HyperTerminal to send keyboard characters to the FPGA. I initially want to relay these hex keyboard codes to the LED’s on the FPGA and later use these codes as input for motor control. The keyboard will be used as input for all of the motors used on a rover.
Here is the code I’ve been working on. I appreciate any assistance.
*I added MOSI section in the code and set tdat to FF
**LED outputs for rdata just switch between FF to 00 depending on the keyboard key pressed.
module SPI_test(
input clk,
input attn,
input miso,
input [7:0] tdat,
output reg ss,
output reg sck,
output reg mosi,
output reg [7:0] rdata,
output ledtest,
output reg ledtest2
);
assign ledtest = ~attn;
//assign ledtest2 = ~ss;
parameter idle = 2'b00;
parameter send = 2'b10;
parameter finish = 2'b11;
reg [1:0] cur;
reg [1:0] nxt;
reg [7:0] rreg, treg;
reg [3:0] nbit;
reg [4:0] mid;
reg [4:0] cnt;
reg shift;
reg clr;
reg [1:0] cdiv = 2'b00;
//FSM i/o
always @ (attn or cur or nbit) begin
nxt <= cur;
clr <= 0;
shift <= 0;
//ss <= 0;
case (cur)
idle: begin
if (attn==0) begin
case (cdiv)
2'b00: mid <= 2;
2'b01: mid <= 4;
2'b10: mid <= 8;
2'b11: mid <= 16;
endcase
shift <= 1;
nxt <= send;
end
end //idle
send: begin
ss <= 0;
if (nbit != 9)
shift <= 1;
else begin
rdata <= rreg;
nxt <= finish;
end
end //send
finish: begin
shift <= 0;
ss <= 1;
clr <= 1;
nxt <= idle;
end
default: nxt <= finish;
endcase
end //always
//state transitions
always @ (negedge clk) begin
cur <= nxt;
end
//Setup clk for read miso
always @ (negedge clk or posedge clr) begin
if (clr == 1) begin
cnt <= 0;
sck <= 1;
end
else begin
if (shift == 1) begin
cnt <= cnt + 1;
if (cnt == mid) begin
sck <= ~sck;
cnt <= 0;
end //mid
end //shift
end //else
end //always
//read miso
always @ (posedge sck or posedge clr) begin
if (clr == 1) begin
nbit <= 0;
rreg <= 8'hFF;
end
else begin
rreg <= {rreg[6:0],miso};
nbit <= nbit + 1;
end
end //always
always@(posedge sck or posedge clr) begin
if(clr==1) begin
treg <= 8'hFF;
mosi <= 1;
end
else begin
if(nbit==0) begin //load data into TREG
treg <= tdat;
mosi <= treg[7];
end //nbit_if
else begin
treg <= {treg[6:0],1'b1};
mosi <= treg[7];
end //else
end //rst
end //always
endmodule